Projeto de diodo de fixação para circuitos de disparo de alta tensão de lâmpadas UV

Projeto de diodo de fixação para circuitos de disparo de alta tensão de lâmpadas UV

Sumário

The trigger stage of a UV curing lamp rings at 200–500 kHz and reflects leakage energy back into the switch at turn-off. This article gives the clamp arithmetic for a 500 V, 40 A trigger primary: the 1.6 mJ per pulse the capacitor must absorb, the 1.1 kV clamp level, the 166 ns core reset, and the four field failure modes that a coupled diode-capacitor-switch design prevents.

1. Introdução

A mercury UV lamp needs an ionizing pulse burst before the arc can hold. The trigger transformer delivers 8–15 kV at 200–500 kHz. Every pulse stresses each unprotected node of the primary circuit.

Field engineers replace the clamp diode, the snubber capacitor and the switch as a set after a failure. The three parts act as one coupled loop. The diode recovery injects current, the capacitor impedance shapes the spike, and the loop inductance sets how much voltage the switch sees.

A trigger network that survives 100,000 starts differs from one that fails at 3,000 in the dimensioning of that loop. The clamp catches the reflected overshoot, resets the transformer core, and limits the voltage at the switching device.

This article gives the arithmetic for the clamp, the four field failure modes, the diode and capacitor selection rules, and the layout limit that holds the residual spike near one tenth of the clamp voltage.

2. Mecanismo Central

2.1 Peak current and leakage energy

During the on-time the switch ramps the primary current from zero. The peak follows the bus voltage, the on-time and the primary inductance.

I_pk = V_bus × t_on / L_p

where I_pk is the peak primary current, V_bus the DC bus voltage, t_on the switch on-time, and L_p the primary magnetizing inductance. At 500 V bus, 1 µs of on-time and L_p = 12.5 µH, the peak reaches 40 A.

The ramp stores most of its energy in the leakage inductance, and only a small part in the core. That energy has to leave the circuit at turn-off.

E_clamp = 0.5 × L_k × I_pk²

where E_clamp is the energy the clamp absorbs per pulse, L_k the leakage inductance referred to the primary, and I_pk the peak primary current. With L_k = 2 µH and I_pk = 40 A, the clamp absorbs 1.6 mJ on every pulse.

2.2 Clamp voltage and the switch rating

At turn-off the primary voltage flies to the bus voltage plus the clamp level. That level follows the leakage ratio and the coupling coefficient.

V_clamp ≈ V_bus × √(L_p / L_k) × k

where V_clamp is the clamp voltage and k the coupling coefficient. With k = 0.9 the clamp settles near 1.1 kV, which is 65% of a 1.7 kV switch rating and inside the 70–80% design limit.

With no clamp the same 1.6 mJ rings the node capacitance. The unclamped peak follows the stored energy and the node capacitance.

V_spike = √(2 × E_clamp / C_node)

where V_spike is the unclamped peak, E_clamp the leakage energy per pulse, and C_node the total capacitance at the drain node. Against 1.4 nF of node capacitance the 1.6 mJ rings to 1.51 kV, which is 2.5× the rating of a 600 V device.

2.3 Reset time and the pulse period

After the diode blocks, the charged clamp capacitor discharges through the primary and returns the core flux to zero. The reset behaves as an LC quarter period.

τ_reset = √(L_p × C_c)

where τ_reset is the reset time constant, L_p the primary inductance, and C_c the clamp capacitance. A 2.2 nF capacitor resets the 12.5 µH primary in 166 ns. The pulse period at 500 kHz is 2 µs, so the core returns to zero with 12× margin.

The reset requirement also caps the capacitor value, because an oversized part slows the next voltage rise.

C_c ≤ 1 / (π² × f_trig² × L_p × k_reset²)

where C_c is the maximum clamp capacitance, f_trig the trigger frequency, and k_reset the reset margin factor. At 500 kHz and L_p = 12.5 µH the ceiling is 32 nF, so a 2.2 nF part sits 15× below it.

2.4 Diode recovery and the residual spike

A slow clamp diode conducts through its reverse-recovery interval. The recovery charge then circulates in the clamp loop and adds a spike on the clamp voltage.

ΔV_res ≈ L_loop × di/dt

where ΔV_res is the residual spike, L_loop the clamp loop inductance, and di/dt the recovery or commutation rate. The trace in the clamp loop adds 8–10 nH per cm, and the transformer leakage adds 2 µH. At 500 A/µs the leakage term alone reaches 1 kV. The layout only trims the last few tens of volts, but those volts decide whether the device survives with margin.

Fig. 1 — The clamp diode and a 2.2 nF Class I capacitor absorb 1.6 mJ per pulse, reset the 12.5 µH primary in 166 ns and hold the switch at 1.1 kV.

3. Pontos problemáticos de engenharia

Pain Point 1: The core walks into saturation and the lamp stops striking

When the clamp capacitor is oversized the magnetizing current never decays to zero between pulses. The flux bias accumulates pulse after pulse. After a few thousand start attempts the core saturates, the primary inductance falls away from 12.5 µH, and the secondary pulse drops below the lamp breakdown threshold.

The controller still commands a trigger. The lamp never strikes, and the fault is found only after hours of troubleshooting.

Pain Point 2: Unclamped leakage destroys the switching device

At 500 V bus, 2 µH of leakage and 40 A peak, the reflected spike reaches about 1.5 kV. That is 2.5× the rating of a 600 V device. The device fails short-circuit and usually takes the gate driver with it.

The failure looks intermittent because it depends on the pulse where the lamp first arcs over.

Pain Point 3: Slow-diode recovery misfires the switch

A standard rectifier in the clamp position conducts during reverse recovery and shorts the reflected pulse. The device overheats, or the recovery spike couples into the gate drive and misfires the switch. The result is erratic ignition and an EMI burst that disturbs the digital controller.

The 2CL rectifier stack that handles the 10 kV output path has a recovery time below 1 µs. That part does not belong in the clamp position, where the requirement is below 50 ns.

Pain Point 4: Capacitor heating and partial-discharge erosion

The clamp capacitor absorbs 1.6 mJ at the trigger rate, which is 1.6 W of average dissipation at 1 kHz. A high-tanδ dielectric runs hot inside the cabinet. A part with a marginal partial-discharge inception voltage erodes over hundreds of thousands of pulses until a tracking failure occurs, often taking the clamp diode out at the same moment.

4. Etapas de projeto

Strategy 1: Set the clamp voltage limit before the capacitor value

Choose V_clamp at 70–80% of the switch rating. For a 1.7 kV device that allows 1.19–1.36 kV, and the 1.1 kV computed in §2.2 fits with margin.

Then size C_c from the reset criterion in §2.3. A 2.2 nF part gives a 166 ns reset against a 2 µs period, and stays 15× below the 32 nF ceiling.

Strategy 2: Use avalanche-rated fast-recovery diodes

Specify t_rr below 50 ns so the recovery charge stays out of the clamp loop. Choose an avalanche-rated part, so an occasional unclamped spike is absorbed in the diode body. Verify the repetitive peak forward current against the 40 A computed in §2.1.

Strategy 3: Put a low-ESL Class I capacitor across the clamp diode

Especificar capacitores disco de cerâmica on N4700 (T3M) strontium titanate dielectric with tanδ below 0.1% and partial discharge below 5 pC at 1.2× rated voltage. The low loss keeps the 1.6 W of snubber dissipation from raising the body temperature.

Size the part so the residual spike from §2.4 stays under 10% of V_clamp. A short internal electrode path keeps the ESL low, which favors disc and screw-terminal construction over long axial leads. A capacitor de filme with less reversal tolerance is the weaker choice at this node, because the clamp branch sees the reflected pulse on every cycle.

Strategy 4: Hold the clamp loop under 2 cm²

Each centimetre of trace adds 8–10 nH. At 500 A/µs a 10 nH trace term contributes 5 V, while the 2 µH transformer leakage contributes 1 kV. The loop area sets the trace term that the rest of the design cannot recover.

Place the clamp recuperação rápida diode and its capacitor on the same side of the board, within 2 cm² of the switch. Route the return directly under the forward path.

Strategy 5: Prove reset and lifetime on the bench

During prototype validation, measure the transformer primary current at the instant the next trigger pulse starts. It must begin from zero. Any residual current means incomplete reset and calls for a smaller C_c.

Then run 100,000 start cycles at the full 1 kHz trigger rate and log the clamp diode and capacitor body temperatures. Accept the design only when both stay inside their rated limits.

Parâmetro do componente	Valor típico	Condição de teste
Tensão reversa de pico repetitiva	VRRM de 10 kV	Série 2CL, 25 °C
Corrente direta média	0.8 A IF(AV)	onda retangular, Tc ≤ 85 °C
corrente de surto direta	100 A a 8.3 ms	surto único, IFSM
Tempo de recuperação reversa	abaixo de 1 µs trr	grau de recuperação suave
Capacitância de junção	25 pF típico.	VR = 4 kV, 1 MHz
Temperatura de operação	-55°C a +125°C	Tj máximo
A corrente de fuga	abaixo de 5 mA no VRRM	25 °C, classificação máxima

5. HVC N4700 capacitors for UV trigger clamps

Three requirements drive the choice at this node: a capacitance that does not drift with cabinet temperature, low loss while absorbing 1.6 mJ per pulse, and a partial-discharge margin that survives millions of ignitions. HVC builds N4700 parts for exactly that set.

Seis parâmetros que importam aqui.

• N4700 (T3M) Class I dielectric on strontium titanate holds ±30 ppm/°C, so the clamp capacitance and the 166 ns reset time stay put from 20 °C to 85 °C.
• tanδ below 0.1% at 1 kHz keeps the snubber part below a few degrees of self-heating at trigger rates up to 1 kHz.
• Voltage ratings from 1 kV to 100 kV cover every trigger design, with the clamp capacitor selectable at 2× voltage margin in the same package outline.
• Guaranteed partial discharge below 5 pC at 1.2× rated voltage, checked on every part, so the clamp site resists PD erosion across millions of pulses.
• Low-ESL disc and capacitores maçaneta packages keep the clamp loop small without exotic layout work.
• Proven in field service: an HVC 40 kV / 441 screw-type capacitor replaced a first-tier brand part in high-voltage field-service programs, and the same PD-screened Class I construction is the standard recommendation for UV trigger clamps. HVC parts match the electrical parameters of Vishay Gama de cabos radiais HVCC e KEMET.
• Above 1 kV the clamp site is available as a series stack, and HVC supplies matching resistores de classificação Assim, a pilha mantém sua divisão de tensão após o ciclo térmico.

Entrega e suporte

Standard parts ship in 4–8 weeks and matched sets in 6–10 weeks. HVC applications engineering supports clamp voltage calculation, capacitor sizing, reset analysis and thermal review for trigger networks.

Send the trigger transformer parameters, bus voltage, switch rating and trigger rate. HVC returns a clamp recommendation with a diode class, a C_c value with reset analysis, and a PD-certified sample for bench testing, typically within two weeks.

6. Perguntas frequentes

Q1: Why does an oversized clamp capacitor stop the lamp from striking?

Because it slows the discharge of the clamp branch past the next pulse. The magnetizing current never reaches zero, the core flux bias accumulates, and after a few thousand starts the core saturates. The primary inductance then falls away from 12.5 µH and the secondary pulse no longer reaches the lamp breakdown threshold.

Q2: How do I choose the clamp capacitor value?

Work from the reset time. C_c must satisfy the reset criterion and keep τ_reset = √(L_p × C_c) well inside the pulse period. For L_p = 12.5 µH at 500 kHz the ceiling is 32 nF, and a 2.2 nF part resets the core in 166 ns with a 12× margin.

Q3: Which diode belongs in the clamp position?

An avalanche-rated fast-recovery part with t_rr below 50 ns and a repetitive peak forward current above the 40 A the primary reaches. A soft-recovery 2CL stack with a recovery time below 1 µs serves the 10 kV output path, and its recovery charge is too large for the clamp loop.

Q4: What spike does an unclamped leakage inductance produce?

At 500 V bus, 2 µH of leakage and 40 A peak, the energy is 1.6 mJ. Against 1.4 nF of node capacitance that rings to 1.51 kV, which is 2.5× the rating of a 600 V switching device. The device fails short-circuit and often destroys the gate driver as well.

Q5: Does PCB layout matter as much as the component choice?

Less than the leakage term. Trace inductance adds 8–10 nH per cm, so a 10 nH loop at 500 A/µs contributes 5 V, while the 2 µH transformer leakage contributes 1 kV. Keep the loop under 2 cm² to remove that 5 V term and to keep the recovery current out of the gate-drive return.

Q6: How is the design verified?

Measure the primary current when the next trigger pulse starts. It must begin from zero, which proves the core reset. Then run 100,000 starts at 1 kHz with the diode and capacitor body temperatures logged, and accept the design only when both stay inside their ratings.

7. Referências

1. E. Kuffel, WS Zaengl, J. Kuffel, Fundamentos de Engenharia de Alta Tensão, 2ª ed., Newnes, 2000.
2. N. Mohan, TM Undeland, WP Robbins, Eletrônica de Potência: Conversores, Aplicações e Projeto, 3ª ed., Wiley, 2003.
3. Aviso MIL-HDBK-217F 2, Previsão da confiabilidade de equipamentos eletrônicos 1995.
4. IEC 60384-1:2018, Capacitores fixos para uso em equipamentos eletrônicos — Parte 1: Especificação genérica.
5. IEC 60270:2025, Técnicas de teste de alta tensão - Medição de descargas parciais baseada em carga, 4ª ed. Genebra: IEC, 2025.
6. IEC 61071:2017, Capacitores para eletrônica de potência, Ed. 2.0. Genebra: Comissão Eletrotécnica Internacional, 2017.
7. Y. Zhou, B. Chen, C. Tian, ​​J. Yuan e Y. Chen, Conversor linear com diodos de fixação em paralelo para teste de resistência e medição de descarga parcial de equipamentos elétricos, Alta Voltagem, vol. 8, nº 1, pp. 171-182, 2023. https://doi.org/10.1049/hve2.12312.
8. AND9800/D — Seleção de capacitor snubber para aplicações de acionamento de motor (Tabela 15 - Dados de teste), onsemi, AND9800-D, https://m.onsemi.jp/pub/Collateral/AND9800-D.PDF .
9. GB/T 7354-2018, 高电压试验技术 局部放电测量. 北京: 中国标准出版社, 2018.
10. Utilizando níveis de baixa tensão para testar capacitores de alta tensão (corrente de fuga), Fórum da Comunidade Eletrônica EEVblog, https://www.eevblog.com/forum/testgear/using-low-voltage-levels-to-test-hv-capacitors-leakage-current/ .
11. Equipe de Engenharia de Aplicações HVC, Capacitor Cerâmico De Alta Tensão Recursos técnicos, https://www.hv-caps.com